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publication# 16492 rev. d amendment /0 issue date: february 1996 2-3 advanced micro devices pal16r8 family 20-pin ttl programmable array logic final com'l: -4/5/7/b/b-2/a, d/2 distinctive characteristics n as fast as 4.5 ns maximum propagation delay n popular 20-pin architectures: 16l8, 16r8, 16r6, 16r4 n programmable replacement for high-speed ttl logic n register preload for testability n power-up reset for initialization n extensive third-party software and programmer support through fusionpld partners n 20-pin dip and plcc packages save space n 28-pin plcc-4 package provides ultra-clean high-speed signals general description the pal16r8 family (pal16l8, pal16r8, pal16r6, pal16r4) includes the pal16r8-5/4 series which pro- vides the highest speed in the 20-pin ttl pal device family, making the series ideal for high-performance ap- plications. the pal16r8 family is provided with stan- dard 20-pin dip and plcc pinouts and a 28-pin plcc pinout. the 28-pin plcc pinout contains seven extra ground pins interleaved between the outputs to reduce noise and increase speed. the devices provide user-programmable logic for re- placing conventional ssi/msi gates and flip-flops at a reduced chip count. the family allows the systems engineer to implement the design on-chip, by opening fuse links to configure and and or gates within the device, according to the desired logic function. complex interconnections be- tween gates, which previously required time-consuming layout, are lifted from the pc board and placed on sili- con, where they can be easily modified during proto- typing or production. the pal device implements the familiar boolean logic transfer function, the sum of products. the pal device is a programmable and array driving a fixed or array. the and array is programmed to create custom product terms, while the or array sums selected terms at the outputs. in addition, the pal device provides the following options: variable input/output pin ratio programmable three-state outputs registers with feedback product terms with all connections opened assume the logical high state; product terms connected to both true and complement of any single input assume the logical low state. registers consist of d-type flip-flops that are loaded on the low-to-high transition of the clock. un- used input pins should be tied to v cc or gnd. the entire pal device family is supported by the fusionpld partners. the pal family is programmed on conventional pal device programmers with appropriate personality and socket adapter modules. once the pal device is programmed and verified, an additional con- nection may be opened to prevent pattern readout. this feature secures proprietary circuits. product selector guide dedicated product terms/ device inputs outputs output feedback enable pal16l8 10 6 comb. 7 i/o prog. 2 comb. 7 C prog. pal16r8 8 8 reg. 8 reg. pin pal16r6 8 6 reg. 8 reg. pin 2 comb. 7 i/o prog. pal16r4 8 4 reg. 8 reg. pin 4 comb. 7 i/o prog.
amd 2-4 pal16r8 family block diagrams 16492d-1 7 7 programmable and array (32 x 64) pal16l8 10 inputs o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 o 8 7 777 77 16492d-2 8 8 o 2 o 3 o 4 o 5 o 6 o 7 o 8 d q q o 1 programmable and array (32 x 64) pal16r8 8 inputs oe clk d q q d q q d q q d q q d q q d q q d q q 8 888 8 8
amd 2-5 pal16r8 family block diagrams 16492d-3 7 8 8 8 8 programmable and array (32 x 64) 8 inputs oe clk pal16r6 o 2 o 3 o 4 o 5 o 6 o 7 i/o 8 q q qq d q 887 i/o 1 q d q d q d q d q q d q d q 7 q programmable and array (32 x 64) oe clk i/o 1 8 pal16r4 i/o 2 i/o 7 i/o 8 o 3 o 4 o 5 o 6 d q q d q q d q q 88887 7 7 16492d-4
amd 2-6 pal16r8 family connection diagrams top view 1 2 3 4 28 27 26 25 5 24 23 22 21 20 19 18 17 16 15 6 7 8 9 10 11 12 13 14 i 8 gnd (note 2) (note 3) gnd (note 4) gnd i 1 (note 1) v cc (note 10) gnd (note 9) gnd (note 8) gnd (note 7) gnd (note 5) gnd (note 6) v cc i 5 i 6 i 7 i 4 i 3 i 2 1 20 19 18 17 16 15 14 2 3 4 5 6 7 8 9 10 11 12 13 i 3 i 4 i 5 i 6 i 7 (note 9) (note 8) (note 7) (note 6) (note 5) (note 2) (note 3) (note 4) gnd i 8 (note 1) v cc (note 10) i 1 i 2 16 14 12 13 19 note 16l8 16r8 16r6 16r4 1i 0 clk clk clk 2i 9 oe oe oe 3o 1 o 1 i/o 1 i/o 1 4 i/o 2 o 2 o 2 i/o 2 5 i/o 3 o 3 o 3 o 3 6 i/o 4 o 4 o 4 o 4 7 i/o 5 o 5 o 5 o 5 8 i/o 6 o 6 o 6 o 6 9 i/o 7 o 7 o 7 i/o 7 10 o 8 o 8 i/o 8 i/o 8 pin designations clk = clock gnd = ground i = input i/o = input/output o = output oe = output enable v cc = supply voltage dip 20-pin plcc (note 1) (note 10) i 1 i 2 i 3 i 4 i 5 i 6 i 7 gnd i 8 (note 9) (note 8) (note 7) (note 5) (note 4) (note 3) (note 2) v cc (note 6) 28-pin plcc note: pin 1 is marked for orientation. 16492d-5 16492d-6 16492d-7 3 5 7 2 1 4 8 6 15 11 9 10 17 18 20
amd 2-7 pal16r8-4/5/7, d/2 (com'l) ordering information commercial products amd programmable logic products for commercial applications are available with several ordering options. the order number (valid combination) is formed by a combination of: valid combinations valid combinations lists configurations planned to be supported in volume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly released combinations. pal 16 r 8 -5 p c family type pal = programmable array logic number of array inputs output type r = registered l = active-low combinatorial number of outputs speed -4 = 4.5 ns t pd -5 = 5 ns t pd -7 = 7.5 ns t pd d = 10 ns t pd package type p = 20-pin plastic dip (pd 020) j = 20-pin plastic leaded chip carrier (pl 020) 28-pin plastic leaded chip carrier for -4 (pl 028) d = 20-pin ceramic dip (cd 020) operating conditions c = commercial (0 c to +75 c) optional processing blank = standard processing pal16l8 -5pc, -5jc, -4jc valid combinations pal16r8 pal16r6 pal16r4 pal16l8-7 pal16r8-7 pal16r6-7 pal16r4-7 pc, jc, dc version blank = first revision /2 = second revision pal16l8d/2 pal16r8d/2 pal16r6d/2 pal16r4d/2 pc, jc
amd 2-8 pal16r8/b/b-2/a/b-4 (com'l) ordering information commercial products (mmi marking only) h. package type n = 20-pin plastic dip (pd 020) nl = 20-pin plastic leaded chip carrier (pl 020) j = 20-pin ceramic dip (cd 020) amd programmable logic products for commercial applications are available with several ordering options. the order number (valid combination) is formed by a combination of: pal16l8 valid combinations valid combinations valid combinations lists configurations planned to be supported in volume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly released combinations. note: marked with mmi logo. pal 16 r 8 b c n pal16r8 pal16r6 pal16r4 a. family type pal = programmable array logic b. number of array inputs c. output type r = registered l = active-low combinatorial d. number of outputs speed b = very high speed (15 nsC35 ns t pd ) a = high speed (25 nsC35 ns t pd ) g. operating conditions c = commercial (0 c to +75 c) i. optional processing blank = standard processing -2 f. power blank = full power (155 maC180 ma i cc ) -2 = half power (80 maC90 ma i cc ) -4 = quarter power (55 ma i cc ) cn, cnl, cj b, b-2, a, b-4
amd 2-9 pal16r8 family functional description standard 20-pin pal family the standard bipolar 20-pin pal family devices have common electrical characteristics and programming procedures. four different devices are available, includ- ing both registered and combinatorial devices. all parts are produced with a fuse link at each input to the and gate array, and connections may be selectively re- moved by applying appropriate voltages to the circuit. utilizing an easily-implemented programming algo- rithm, these products can be rapidly programmed to any customized pattern. extra test words are pre- programmed during manufacturing to ensure extremely high field programming yields, and provide extra test paths to achieve excellent parametric correlation. pinouts the pal16r8 family is available in the standard 20-pin dip and plcc pinouts and the pal16r8-4 series is available in the new 28-pin plcc pinout. the 28-pin plcc pinout gives the designer the cleanest possible signal with only 4.5 ns delay. the pal16r8-4 pinout has been designed to minimize the noise that can be generated by high-speed signals. because of its inherently shorter leads, the plcc pack- age is the best package for use in high-speed designs. the short leads and multiple ground signals reduce the effective lead inductance, minimizing ground bounce. placing the ground pins between the outputs optimizes the ground bounce protection, and also isolates the out- puts from each other, eliminating cross-talk. this pinout can reduce the effective propagation delay by as much as 20% from a standard dip pinout. design files for pal16r8-4 series devices are written as if the device had a standard 20-pin dip pinout for most design soft- ware packages. variable input/output pin ratio the registered devices have eight dedicated input lines, and each combinatorial output is an i/o pin. the pal16l8 has ten dedicated input lines and six of the eight combinatorial outputs are i/o pins. buffers for de- vice inputs have complementary outputs to provide user-programmable input signal polarity. unused input pins should be tied to v cc or gnd. programmable three-state outputs each output has a three-state output buffer with three- state control. on combinatorial outputs, a product term controls the buffer, allowing enable and disable to be a function of any product of device inputs or output feed- back. the combinatorial output provides a bidirectional i/o pin and may be configured as a dedicated input if the output buffer is always disabled. on registered outputs, an input pin controls the enabling of the three-state outputs. registers with feedback registered outputs are provided for data storage and synchronization. registers are composed of d-type flip-flops that are loaded on the low-to-high transition of the clock input. register preload the register on the amd marked 16r8, 16r6, and 16r4 devices can be preloaded from the output pins to facili- tate functional testing of complex state machine de- signs. this feature allows direct loading of arbitrary states, making it unnecessary to cycle through long test vector sequences to reach a desired state. in addition, transitions from illegal states can be verified by loading illegal states and observing proper recovery. power-up reset all flip-flops power-up to a logic low for predictable system initialization. outputs of the pal16r8 family will be high due to the active-low outputs. the v cc rise must be monotonic and the reset delay time is 1000 ns maximum. security fuse after programming and verification, a pal16r8 family design can be secured by programming the security fuse. once programmed, this fuse defeats readback of the internal programmed pattern by a device program- mer, securing proprietary designs from competitors. when the security fuse is programmed, the array will read as if every fuse is programmed. quality and testability the pal16r8 family offers a very high level of built-in quality. extra programmable fuses provide a means of verifying performance of all ac and dc parameters. in addition, this verifies complete programmability and functionality of the device to provide the highest pro- gramming yields and post-programming functional yields in the industry. technology the pal16r8-5, -7 and d/2 are fabricated with amd's oxide isolated bipolar process. the array connections are formed with highly reliable ptsi fuses. the pal16r8b, b-2, a and b-4 series are fabricated with amd's advanced trench-isolated bipolar process. the array connections are formed with proven tiw fuses for reliable operation. these processes reduce parasitic capacitances and minimum geometries to provide higher performance.
amd 2-10 pal16r8 family logic diagram dip and 20-pin plcc (28-pin plcc) pinouts 16492d-8 0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 0 7 0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 8 15 16 23 24 31 32 39 40 47 48 55 56 63 i 0 i 1 i 3 i 4 i 5 i 6 i 7 i 8 i 2 o 8 i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 o 1 11 i 9 gnd v cc 1 2 3 4 5 6 7 8 9 12 13 14 16 17 18 19 (24) (25) (26) (27) (28) v cc (1) (2) (3) (4) (5) (6) (22) (21) (20) (18) (16) (14) (12) (10) (8) (7) gnd (19) gnd (17) gnd (15) gnd 15 (13) gnd (11) gnd (9) gnd (23) 20 16l8-5 (-4) 10 16l8 (-4)
amd 2-11 pal16r8 family logic diagram dip and 20-pin plcc (28-pin plcc) pinouts 16492d-9 0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 0 7 0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 8 15 16 23 24 31 32 39 40 47 48 55 56 63 16r8-5 (-4) 2 3 4 5 6 7 8 9 1 18 d q q 19 17 16 15 14 13 12 11 o 8 o 7 o 6 o 5 o 4 o 3 o 2 o 1 oe v clk i 1 i 2 i 3 i 4 i 5 i 6 i 7 i 8 d q q v d q q v d q q v d q q v d q q v d q q v d q q v gnd v cc (21) gnd (23) (22) (20) (17) gnd (18) (16) (15) gnd (14) gnd (11) (12) gnd (13) (10) gnd (9) (8) (7) (6) (5) (4) (3) (2) v cc (1) (28) (27) (26) (25) (24) (19) gnd 10 20 16r8 (-4)
amd 2-12 pal16r8 family logic diagram dip and 20-pin plcc (28-pin plcc) pinouts 0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 0 7 0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 8 15 16 23 24 31 32 39 40 47 48 55 56 63 16r6-5 (-4) 2 3 4 6 7 9 10 1 18 d q q 19 17 16 15 14 13 12 11 i/o 8 o 7 o 6 o 5 o 4 o 3 o 2 i/o 1 oe v clk i 1 i 2 i 3 i 4 i 5 i 6 i 7 i 8 d q q v d q q v d q q v d q q v d q q v gnd (22) v cc (23) (17) gnd (21) gnd (20) (18) (19) gnd (16) (15) gnd (14) (13) gnd (12) (11) gnd (10) (9) gnd (8) (7) v cc (1) (28) 5 (6) (5) (4) (3) (2) (27) (26) (25) (24) 8 20 16r6 (-4) 16492d-10
amd 2-13 pal16r8 family logic diagram dip and 20-pin plcc (28-pin plcc) pinouts 0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 0 7 0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 8 15 16 23 24 31 32 39 40 47 48 55 56 63 16r4-5 (-4) 1 clk i 1 i 3 i 4 i 5 i 6 i 7 i 8 i 2 i/o 8 i/o 7 o 6 o 5 o 4 o 3 i/o 2 i/o 1 oe gnd v cc 2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18 19 d q q v d q q v d q q v d q q v (6) (19) gnd (23) (22) (20) (21) gnd (18) (17) gnd (16) (14) gnd (15) gnd (13) (12) gnd (11) (10) gnd (9) (8) (7) (5) (4) (3) (2) v cc (1) (28) (27) (26) (25) (24) 10 20 16r4 (-4) 16492d-11
amd 2-14 pal16r8-4/5 (com'l) parameter symbol parameter description test conditions min max unit v oh output high voltage i oh = C3.2 ma v in = v ih or v il 2.4 v v cc = min v ol output low voltage i ol = 24 ma v in = v ih or v il 0.5 v v cc = min v ih input high voltage guaranteed input logical high 2.0 v voltage for all inputs (note 1) v il input low voltage guaranteed input logical low 0.8 v voltage for all inputs (note 1) v i input clamp voltage i in = C18 ma, v cc = min C1.2 v i ih input high current v in = 2.7 v, v cc = max (note 2) 25 m a i il input low current v in = 0.4 v, v cc = max (note 2) C250 m a i i maximum input current v in = 5.5 v, v cc = max 1 ma i ozh off-state output leakage v out = 2.7 v, v cc = max 100 m a current high v in = v ih or v il (note 2) i ozl off-state output leakage v out = 0.4 v, v cc = max C100 m a current low v in = v ih or v il (note 2) i sc output short-circuit current v out = 0.5 v, v cc = max (note 3) C30 C130 ma i cc supply current v in = 0 v, outputs open (i out = 0 ma) 210 ma v cc = max dc characteristics over commercial operating ranges unless otherwise specified absolute maximum ratings ambient temperature with power applied C65 c to +150 c . . . . . . . . . . . . . . . storage temperature C55 c to +125 c . . . . . . . . . . supply voltage with respect to ground C0.5 v to + 7.0 v . . . . . . . . . . . . . dc input voltage C1.2 v to v cc + 0.5 v . . . . . . . . . . dc input current C30 ma to + 5 ma . . . . . . . . . . . . . dc output or i/o pin voltage C0.5 v to v cc + 0.5 v . . . . . . . . . . . . . . . . . . static discharge voltage 2001 v . . . . . . . . . . . . . . . stresses above those listed under absolute maximum rat- ings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maxi- mum ratings for extended periods may affect device reliabil- ity. programming conditions may differ. operating ranges commercial (c) devices ambient temperature (t a ) operating in free air 0 c to +75 c . . . . . . . . . . . . . . . supply voltage (v cc ) with respect to ground +4.75 v to +5.25 v . . . . . . . . . operating ranges define those limits between which the func- tionality of the device is guaranteed. notes: 1. these are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. i/o pin leakage is the worst case of i il and i ozl (or i ih and i ozh ). 3. not more than one output should be tested at a time. duration of the short-circuit should not exceed one second. v out = 0.5 v has been chosen to avoid test problems caused by tester ground degradation.
amd 2-15 pal16r8-4/5 (com'l) parameter symbol parameter description test conditions typ unit c in input capacitance v in = 2.0 v v cc = 5.0 v 8 5 c out output capacitance v out = 2.0 v f = 1 mhz 8 note: 1. these parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. parameter min min symbol parameter description (note 3) max (note 3) max unit t pd input or feedback to combinatorial output 1 5 1 4.5 ns t s setup time from input or feedback to clock 4.5 4.5 ns t h hold time 0 0 ns t co clock to output 1 4.0 1 3.5 ns t skewr skew between registered outputs (note 4) 1 0.5 ns t wl low 4 4 ns t wh high 4 4 ns external feedback 1/(t s + t co ) 117 125 mhz internal feedback 1/(t s + t cf ) 125 125 mhz (f cnt ) (note 6) no feedback 1/(t wh + t wl ) 125 125 mhz t pzx oe to output enable 1 6.5 1 6.5 ns t pxz oe to output disable 1 5 1 5 ns t ea input to output enable using 2 6.5 2 6.5 ns product term control t er input to output disable using 2 5 2 5 ns product term control capacitance (note 1) switching characteristics over commercial operating ranges (note 2) t a = 25 c pf clock width maximum frequency (note 5) f max -5 -4 notes: 2. see switching test circuit for test conditions. 3. output delay minimums for t pd , t co , t pzx , t pxz , t ea , and t er are defined under best case conditions. future process improve- ments may alter these values; therefore, minimum values are recommended for simulation purposes only. 4. skew testing takes into account pattern and switching direction differences between outputs. 5. these parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where the frequency may be affected. 6. t cf is a calculated value and is not guaranteed. t cf can be found using the following equation: t cf = 1/f max (internal feedback) C t s . 16r8, 16r6, 16r4 16l8, 16r6, 16r4 16l8, 16r8, 16r4 clk, oe i 1 Ci 8
amd 2-16 pal16r8-7 (com'l) absolute maximum ratings storage temperature C65 c to +150 c . . . . . . . . . . . ambient temperature with power applied C55 c to +125 c . . . . . . . . . . . . . . . . . supply voltage with respect to ground C0.5 v to + 7.0 v . . . . . . . . . . . . . dc input voltage C1.2 v to + 7.0 v . . . . . . . . . . . . . . . dc input current C30 ma to + 5 ma . . . . . . . . . . . . . . dc output or i/o pin voltage C0.5 v to v cc + 0.5 v . . . . . . . . . . . . . . . . . . static discharge voltage 2001 v . . . . . . . . . . . . . . . . . stresses above those listed under absolute maximum rat- ings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maxi- mum ratings for extended periods may affect device reliabil- ity. programming conditions may differ. operating ranges commercial (c) devices ambient temperature (t a ) operating in free air 0 c to +75 c . . . . . . . . . . . . . . supply voltage (v cc ) with respect to ground +4.75 v to +5.25 v . . . . . . . . operating ranges define those limits between which the func- tionality of the device is guaranteed. dc characteristics over commercial operating ranges unless otherwise specified parameter symbol parameter description test conditions min max unit v oh output high voltage i oh = C3.2 ma v in = v ih or v il 2.4 v v cc = min v ol output low voltage i ol = 24 ma v in = v ih or v il 0.5 v v cc = min v ih input high voltage guaranteed input logical high 2.0 v voltage for all inputs (note 1) v il input low voltage guaranteed input logical low 0.8 v voltage for all inputs (note 1) v i input clamp voltage i in = C18 ma, v cc = min C1.2 v i ih input high current v in = 2.7 v, v cc = max (note 2) 25 m a i il input low current v in = 0.4 v, v cc = max (note 2) C250 m a i i maximum input current v in = 5.5 v, v cc = max 1 ma i ozh off-state output leakage v out = 2.7 v, v cc = max 100 m a current high v in = v ih or v il (note 2) i ozl off-state output leakage v out = 0.4 v, v cc = max C100 m a current low v in = v ih or v il (note 2) i sc output short-circuit current v out = 0.5 v, v cc = max (note 3) C30 C130 ma i cc supply current v in = 0 v, outputs open (i out = 0 ma) 180 ma v cc = max notes: 1. these are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. i/o pin leakage is the worst case of i il and i ozl (or i ih and i ozh ). 3. not more than one output should be tested at a time. duration of the short-circuit should not exceed one second. v out = 0.5 v has been chosen to avoid test problems caused by tester ground degradation.
amd 2-17 pal16r8-7 (com'l) capacitance (note 1) parameter symbol parameter description test conditions typ unit c in input capacitance v in = 2.0 v 5 c out output capacitance v out = 2.0 v 8 v cc = 5.0 v t a = 25 c f = 1 mhz pf note: 1. these parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. switching characteristics over commercial operating ranges (note 2) parameter min symbol parameter description (note 3) max unit 16l8, 16r6, 3 7.5 16r4 3 7 t s setup time from input or feedback to clock 7 ns t h hold time 0ns t co clock to output 1 6.5 ns t skew skew between registered outputs (note 4) 16r8, 16r6, 1 ns t wl low 16r4 5 ns t wh high 5 ns external feedback 1/(t s + t co ) 74 mhz f max internal feedback 1/(t s + t cf ) 100 mhz (f cnt ) (note 6) no feedback 1/(t wh + t wl ) 100 mhz t pzx oe to output enable 1 8 ns t pxz oe to output disable 1 8 ns t ea input to output enable using product term control 16l8, 16r6, 3 10 ns t er input to output disable using product term control 16r4 3 10 ns ns maximum frequency (note 5) clock width t pd input or feedback to combinatorial output 1 output switching notes: 2. see switching test circuit for test conditions. 3. output delay minimums for t pd , t co , t pzx , t pxz , t ea , and t er are defined under best case conditions. future process improve- ments may alter these values; therefore, minimum values are recommended for simulation purposes only. 4. skew is measured with all outputs switching in the same direction. 5. these parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where the frequency may be affected. 6. t cf is a calculated value and is not guaranteed. t cf can be found using the following equation: t cf = 1/f max (internal feedback) C t s .
amd 2-18 pal16r8d/2 (com'l) absolute maximum ratings storage temperature C65 c to +150 c . . . . . . . . . . . ambient temperature with power applied C55 c to +125 c . . . . . . . . . . . . . . . . . supply voltage with respect to ground C0.5 v to + 7.0 v . . . . . . . . . . . . . dc input voltage C1.5 v to + 5.5 v . . . . . . . . . . . . . . . dc output or i/o pin voltage C0.5 v to + 5.5 v . . . . . static discharge voltage 2001 v . . . . . . . . . . . . . . . . . stresses above those listed under absolute maximum rat- ings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maxi- mum ratings for extended periods may affect device reliabil- ity. programming conditions may differ. operating ranges commercial (c) devices ambient temperature (t a ) operating in free air 0 c to +75 c . . . . . . . . . . . . . . supply voltage (v cc ) with respect to ground +4.75 v to +5.25 v . . . . . . . . operating ranges define those limits between which the func- tionality of the device is guaranteed. dc characteristics over commercial operating ranges unless otherwise specified parameter symbol parameter description test conditions min max unit v oh output high voltage i oh = C3.2 ma v in = v ih or v il 2.4 v v cc = min v ol output low voltage i ol = 24 ma v in = v ih or v il 0.5 v v cc = min v ih input high voltage guaranteed input logical high 2.0 v voltage for all inputs (note 1) v il input low voltage guaranteed input logical low 0.8 v voltage for all inputs (note 1) v i input clamp voltage i in = C18 ma, v cc = min C1.5 v i ih input high current v in = 2.4 v, v cc = max (note 2) 25 m a i il input low current v in = 0.4 v, v cc = max (note 2) C250 m a i i maximum input current v in = 5.5 v, v cc = max 100 m a i ozh off-state output leakage v out = 2.4 v, v cc = max 100 m a current high v in = v ih or v il (note 2) i ozl off-state output leakage v out = 0.4 v, v cc = max C100 m a current low v in = v ih or v il (note 2) i sc output short-circuit current v out = 0.5 v, v cc = max (note 3) C30 C130 ma i cc supply current v in = 0 v, outputs open (i out = 0 ma) 180 ma v cc = max notes: 1. these are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. i/o pin leakage is the worst case of i il and i ozl (or i ih and i ozh ). 3. not more than one output should be tested at a time. duration of the short-circuit should not exceed one second. v out = 0.5 v has been chosen to avoid test problems caused by tester ground degradation.
amd 2-19 pal16r8d/2 (com'l) capacitance (note 1) parameter symbol parameter description test conditions typ unit c in input capacitance v in = 2.0 v v cc = 5.0 v 5 c out output capacitance v out = 2.0 v f = 1 mhz 8 note: 1. these parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. t a = 25 c pf switching characteristics over commercial operating ranges (note 2) parameter min symbol parameter description (note 3) max unit t pd input or feedback to combinatorial output 16l8, 16r6, 3 10 ns 16r4 t s setup time from input or feedback to clock 10 ns t h hold time 0ns t co clock to output 3 7 ns t wl clock width low 8 ns t wh high 16r8, 16r6, 8 ns external feedback 1/(t s + t co ) 16r4 58.8 mhz f max internal feedback 1/(t s + t cf ) 60 mhz (f cnt ) (note 5) no feedback 1/(t wh + t wl ) 62.5 mhz t pzx oe to output enable 2 10 ns t pxz oe to output disable 2 10 ns t ea input to output enable using product term control 16l8, 16r6, 3 10 ns t er input to output disable using product term control 16r4 3 10 ns maximum frequency (note 4) notes: 2. see switching test circuit for test conditions. 3. output delay minimums for t pd , t co , t pzx , t pxz , t ea , and t er are defined under best case conditions. future process improve- ments may alter these values; therefore, minimum values are recommended for simulation purposes only. 4. these parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where the frequency may be affected. 5. t cf is a calculated value and is not guaranteed. t cf can be found using the following equation: t cf = 1/f max (internal feedback) C t s .
amd 2-20 pal16r8b (com'l) absolute maximum ratings storage temperature C65 c to +150 c . . . . . . . . . . . ambient temperature with power applied C55 c to +125 c . . . . . . . . . . . . . . . . . supply voltage with respect to ground C0.5 v to +7.0 v . . . . . . . . . . . . . dc input voltage C1.5 v to v cc + 0.5 v . . . . . . . . . . . dc output or i/o pin voltage C0.5 v to v cc + 0.5 v . . . . . . . . . . . . . . . . . . stresses above those listed under absolute maximum rat- ings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maxi- mum ratings for extended periods may affect device reliabil- ity. programming conditions may differ. operating ranges commercial (c) devices ambient temperature (t a ) operating in free air 0 c to +75 c . . . . . . . . . . . . . . supply voltage (v cc ) with respect to ground +4.75 v to +5.25 v . . . . . . . . operating ranges define those limits between which the func- tionality of the device is guaranteed. dc characteristics over commercial operating ranges unless otherwise specified parameter symbol parameter description test conditions min max unit v oh output high voltage i oh = C3.2 ma v in = v ih or v il 2.4 v v cc = min v ol output low voltage i ol = 24 ma v in = v ih or v il 0.5 v v cc = min v ih input high voltage guaranteed input logical high 2.0 v voltage for all inputs (note 1) v il input low voltage guaranteed input logical low 0.8 v voltage for all inputs (note 1) v i input clamp voltage i in = C18 ma, v cc = min C1.2 v i ih input high current v in = 2.4 v, v cc = max (note 2) 25 m a i il input low current v in = 0.4 v, v cc = max (note 2) C250 m a i i maximum input current v in = 5.5 v, v cc = max 100 m a i ozh off-state output leakage v out = 2.4 v, v cc = max 100 m a current high v in = v ih or v il (note 2) i ozl off-state output leakage v out = 0.4 v, v cc = max C100 m a current low v in = v ih or v il (note 2) i sc output short-circuit current v out = 0.5 v, v cc = max (note 3) C30 C130 ma i cc supply current v in = 0 v, outputs open (i out = 0 ma) 180 ma v cc = max notes: 1. these are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. i/o pin leakage is the worst case of i il and i ozl (or i ih and i ozh ). 3. not more than one output should be tested at a time. duration of the short-circuit should not exceed one second. v out = 0.5 v has been chosen to avoid test problems caused by tester ground degradation.
amd 2-21 pal16r8b (com'l) capacitance (note 1) parameter symbol parameter description test conditions typ unit c in input capacitance v in = 2.0 v v cc = 5.0 v 8 c out output capacitance v out = 2.0 v f = 1 mhz 9 t a = 25 c pf note: 1. these parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. switching characteristics over commercial operating ranges (note 2) parameter symbol parameter description min max unit t pd input or feedback to combinatorial output 16l8, 16r6, 15 ns 16r4 t s setup time from input or feedback to clock 15 ns t h hold time 0ns t co clock to output or feedback 12 ns t wl clock width low 10 ns t wh high 10 ns maximum external feedback 1/(t s + t co ) 37 mhz f max frequency (note 3) no feedback 1/(t wh + t wl ) 50 mhz t pzx oe to output enable 15 ns t pxz oe to output disable 15 ns t ea input to output enable using product term control 15 ns t er input to output disable using product term control 15 ns 16r8, 16r6, 16r4 16r8, 16r6, 16r4 notes: 2. see switching test circuit for test conditions. 3. these parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected.
amd 2-22 pal16r8b-2 (com'l) absolute maximum ratings storage temperature C65 c to +150 c . . . . . . . . . . . ambient temperature with power applied C55 c to +125 c . . . . . . . . . . . . . . . . . supply voltage with respect to ground C0.5 v to +7.0 v . . . . . . . . . . . . . dc input voltage C1.5 v to v cc + 0.5 v . . . . . . . . . . . dc output or i/o pin voltage C0.5 v to v cc + 0.5 v . . . . . . . . . . . . . . . . . . stresses above those listed under absolute maximum rat- ings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maxi- mum ratings for extended periods may affect device reliabil- ity. programming conditions may differ. operating ranges commercial (c) devices ambient temperature (t a ) operating in free air 0 c to +75 c . . . . . . . . . . . . . . supply voltage (v cc ) with respect to ground +4.75 v to +5.25 v . . . . . . . . operating ranges define those limits between which the func- tionality of the device is guaranteed. dc characteristics over commercial operating ranges unless otherwise specified parameter symbol parameter description test conditions min max unit v oh output high voltage i oh = C3.2 ma v in = v ih or v il 2.4 v v cc = min v ol output low voltage i ol = 24 ma v in = v ih or v il 0.5 v v cc = min v ih input high voltage guaranteed input logical high 2.0 v voltage for all inputs (note 1) v il input low voltage guaranteed input logical low 0.8 v voltage for all inputs (note 1) v i input clamp voltage i in = C18 ma, v cc = min C1.2 v i ih input high current v in = 2.7 v, v cc = max (note 2) 25 m a i il input low current v in = 0.4 v, v cc = max (note 2) C100 m a i i maximum input current v in = 5.5 v, v cc = max 100 m a i ozh off-state output leakage v out = 2.7 v, v cc = max 100 m a current high v in = v ih or v il (note 2) i ozl off-state output leakage v out = 0.4 v, v cc = max C100 m a current low v in = v ih or v il (note 2) i sc output short-circuit current v out = 0.5 v, v cc = max (note 3) C30 C130 ma i cc supply current v in = 0 v, outputs open (i out = 0 ma) 90 ma v cc = max notes: 1. these are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. i/o pin leakage is the worst case of i il and i ozl (or i ih and i ozh ). 3. not more than one output should be tested at a time. duration of the short-circuit should not exceed one second. v out = 0.5 v has been chosen to avoid test problems caused by tester ground degradation.
amd 2-23 pal16r8b-2 (com'l) capacitance (note 1) parameter symbol parameter description test conditions typ unit c in input capacitance v in = 2.0 v v cc = 5.0 v 7 c out output capacitance v out = 2.0 v f = 1 mhz 7 t a = 25 c pf note: 1. these parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. switching characteristics over commercial operating ranges (note 2) parameter symbol parameter description min max unit t pd input or feedback to combinatorial output 16l8, 16r6, 25 ns 16r4 t s setup time from input or feedback to clock 25 ns t h hold time 0ns t co clock to output 15 ns t wl clock width low 15 ns t wh high 15 ns external feedback 1/(t s + t co ) 25 mhz f max internal feedback 1/(t s + t cf ) 28.5 mhz (f cnt ) (note 5) no feedback 1/(t wh + t wl ) 33 mhz t pzx oe to output enable 20 ns t pxz oe to output disable 20 ns t ea input to output enable using product term control 25 ns t er input to output disable using product term control 25 ns maximum frequency (note 4) 16r8, 16r6, 16r4 16r8, 16r6, 16r4 notes: 2. see switching test circuit for test conditions. 3. calculated from measured f max internal. 4. these parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. 5. t cf is a calculated value and is not guaranteed. t cf can be found using the following equation: t cf = 1/f max (internal feedback) C t s .
amd 2-24 pal16r8a (com'l) absolute maximum ratings storage temperature C65 c to +150 c . . . . . . . . . . . ambient temperature with power applied C55 c to +125 c . . . . . . . . . . . . . . . . . supply voltage with respect to ground C0.5 v to + 7.0 v . . . . . . . . . . . . . dc input voltage C1.5 v to v cc + 0.5 v . . . . . . . . . . . dc output or i/o pin voltage C0.5 v to v cc + 0.5 v . . . . . . . . . . . . . . . . . . stresses above those listed under absolute maximum rat- ings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maxi- mum ratings for extended periods may affect device reliabil- ity. programming conditions may differ. operating ranges commercial (c) devices ambient temperature (t a ) operating in free air 0 c to +75 c . . . . . . . . . . . . . . supply voltage (v cc ) with respect to ground +4.75 v to +5.25 v . . . . . . . . operating ranges define those limits between which the func- tionality of the device is guaranteed. dc characteristics over commercial operating ranges unless otherwise specified parameter symbol parameter description test conditions min max unit v oh output high voltage i oh = C3.2 ma v in = v ih or v il 2.4 v v cc = min v ol output low voltage i ol = 24 ma v in = v ih or v il 0.5 v v cc = min v ih input high voltage guaranteed input logical high 2.0 v voltage for all inputs (note 1) v il input low voltage guaranteed input logical low 0.8 v voltage for all inputs (note 1) v i input clamp voltage i in = C18 ma, v cc = min C1.2 v i ih input high current v in = 2.7 v, v cc = max (note 2) 25 m a i il input low current v in = 0.4 v, v cc = max (note 2) C250 m a i i maximum input current v in = 5.5 v, v cc = max 100 m a i ozh off-state output leakage v out = 2.7 v, v cc = max 100 m a current high v in = v ih or v il (note 2) i ozl off-state output leakage v out = 0.4 v, v cc = max C100 m a current low v in = v ih or v il (note 2) i sc output short-circuit current v out = 0.5 v, v cc = max (note 3) C30 C130 ma 16l8 v in = 0 v, outputs open (i out = 0 ma) 155 ma 16r8/6/4 v cc = max 180 i cc supply current notes: 1. these are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. i/o pin leakage is the worst case of i il and i ozl (or i ih and i ozh ). 3. not more than one output should be tested at a time. duration of the short-circuit should not exceed one second. v cc = 0.5 v has been chosen to avoid test problems caused by tester ground degradation.
amd 2-25 pal16r8a (com'l) capacitance (note 1) parameter symbol parameter description test conditions typ unit c in input capacitance v in = 2.0 v v cc = 5.0 v 7 c out output capacitance v out = 2.0 v f = 1 mhz 7 t a = 25 c pf note: 1. these parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. switching characteristics over commercial operating ranges (note 2) parameter symbol parameter description min max unit t pd input or feedback to combinatorial output 16l8, 16r6, 25 ns 16r4 t s setup time from input or feedback to clock 25 ns t h hold time 0ns t co clock to output 15 ns t wl clock width low 15 ns t wh high 15 ns external feedback 1/(t s + t co ) 25 mhz f max internal feedback 1/(t s + t cf ) 28.5 mhz (f cnt ) (note 5) no feedback 1/(t wh + t wl ) 33 mhz t pzx oe to output enable 20 ns t pxz oe to output disable 20 ns t ea input to output enable using product term control 25 ns t er input to output disable using product term control 25 ns maximum frequency (note 4) 16r8, 16r6, 16r4 16r8, 16r6, 16r4 notes: 2. see switching test circuit for test conditions. 3. calculated from measured f max internal. 4. these parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. 5. t cf is a calculated value and is not guaranteed. t cf can be found using the following equation: t cf = 1/f max (internal feedback) C t s .
amd 2-26 pal16r8b-4 (com'l) absolute maximum ratings storage temperature C65 c to +150 c . . . . . . . . . . . ambient temperature with power applied C55 c to +125 c . . . . . . . . . . . . . . . . . supply voltage with respect to ground C0.5 v to +7.0 v . . . . . . . . . . . . . dc input voltage C1.5 v to +5.5 v . . . . . . . . . . . . . . . dc output or i/o pin voltage 5.5 v . . . . . . . . . . . . . . stresses above those listed under absolute maximum rat- ings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maxi- mum ratings for extended periods may affect device reliabil- ity. programming conditions may differ. operating ranges commercial (c) devices ambient temperature (t a ) operating in free air 0 c to +75 c . . . . . . . . . . . . . . supply voltage (v cc ) with respect to ground +4.75 v to +5.25 v . . . . . . . . operating ranges define those limits between which the func- tionality of the device is guaranteed. dc characteristics over commercial operating ranges unless otherwise specified parameter symbol parameter description test conditions min max unit v oh output high voltage i oh = C1 ma v in = v ih or v il 2.4 v v cc = min v ol output low voltage i ol = 8 ma v in = v ih or v il 0.5 v v cc = min v ih input high voltage guaranteed input logical high 2.0 v voltage for all inputs (note 1) v il input low voltage guaranteed input logical low 0.8 v voltage for all inputs (note 1) v i input clamp voltage i in = C18 ma, v cc = min C1.5 v i ih input high current v in = 2.4 v, v cc = max (note 2) 25 m a i il input low current v in = 0.4 v, v cc = max (note 2) C250 m a i i maximum input current v in = 5.5 v, v cc = max 100 m a i ozh off-state output leakage v out = 2.4 v, v cc = max 100 m a current high v in = v ih or v il (note 2) i ozl off-state output leakage v out = 0.4 v, v cc = max C100 m a current low v in = v ih or v il (note 2) i sc output short-circuit current v out = 0.5 v, v cc = max (note 3) C30 C250 ma i cc supply current v in = 0 v, outputs open (i out = 0 ma) 55 ma v cc = max notes: 1. these are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. i/o pin leakage is the worst case of i il and i ozl (or i ih and i ozh ). 3. not more than one output should be tested at a time. duration of the short-circuit should not exceed one second. v out = 0.5 v as been chosen to avoid test problems caused by tester ground degradation.
amd 2-27 pal16r8b-4 (com'l) switching characteristics over commercial operating ranges (note 1) parameter symbol parameter description min max unit t pd input or feedback to combinatorial output 16l8, 16r6, 35 ns 16r4 t s setup time from input or feedback to clock 35 ns t h hold time 0ns t co clock to output or feedback 16r8, 16r6, 25 ns t wl clock width low 16r4 25 ns t wh high 25 ns maximum external feedback 1/(t s + t co ) 16 mhz f max frequency (note 2) no feedback 1/(t wh + t wl ) 20 mhz t pzx oe to output enable 25 ns t pxz oe to output disable 25 ns t ea input to output enable using product term control 16l8, 16r6, 35 ns t er input to output disable using product term control 16r4 35 ns notes: 1. see switching test circuit for test conditions. 2. these parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected.
amd 2-28 pal16r8 family switching waveforms t pd input or feedback combinatorial output v t v t combinatorial output v t input or feedback registered output registered output t s t co v t t h v t clock v t t wh clock clock width t wl clock t skewr v t v t registered output 1 registered output 2 registered output skew notes: 1. v t = 1.5 v 2. input pulse amplitude 0 v to 3.0 v 3. input rise and fall times 2 nsC3 ns typical. v t v t input output input to output disable/enable t er t ea v t v t oe output oe to output disable/enable t pzx t pxz v oh C 0.5v v ol + 0.5v v oh C 0.5v v ol + 0.5v 16492d-12 16492d-13 16492d-14 16492d-15 16492d-16 16492d-17
amd 2-29 pal16r8 family key to switching waveforms ks000010-pal must be steady may change from h to l may change from l to h does not apply don't care, any change permitted will be steady will be changing from h to l will be changing from l to h changing, state unknown center line is high- impedance off state waveform inputs outputs switching test circuit c l output r 1 r 2 s 1 test point 5 v 16492d-18 measured specification s 1 c l r 1 r 2 output value t pd , t co closed all but b-4: all but b-4: 1.5 v t pzx , t ea z ? h: open 50 pf 200 w 390 w 1.5 v z ? l: closed t pxz , t er h ? z: open 5 pf b-4: b-4: h ? z: v oh C 0.5 v l ? z: closed 800 w 1.56 k w l ? z: v ol + 0.5 v commercial
amd 2-30 pal16r8-5 measured switching characteristics for the pal16r8-5 v cc = 4.75 v, t a = 75 c (note 1) t pd vs. number of outputs switching t pd vs. load capacitance v cc = 5.25 v, t a = 25 c note : 1. these parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where t pd may be affected. 5.0 4.5 4.0 3.5 3.0 12345678 t pd , ns number of outputs switching 10 8 6 4 2 0 50 100 t pd , ns 150 200 250 C5 c l , pf C5 16492d-19 16492d-20
amd 2-31 pal16r8-5 current vs. voltage (i-v) characteristics for the pal16r8-4/5 v cc = 5.0 v, t a = 25 c 15 10 output, low i ol , ma 5 C5 C10 C15 C0.6 C0.4 C0.2 0.2 0.4 0.6 v ol , v 20 C40 C60 C80 C3 C2 C1 123 output, high i oh , ma v oh , v C20 input i i , m a v i , v 20 C100 C150 C200 C3 C2 C1 123 C50 C90 16492d-21 16492d-22 16492d-23
amd 2-32 pal16r8-7 measured switching characteristics for the pal16r8-7 v cc = 4.75 v, t a = 75 c (note 1) 7.5 7 6.5 6 1 2 34 5 6 78 number of outputs switching t pd vs. number of outputs switching 8 7 6 5 10 30 50 70 c l , pf t pd , ns t pd , ns 90 110 t pd vs. load capacitance note : 1. these parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where t pd may be affected. 16492d-24 16492d-25
amd 2-33 pal16r8-7 current vs. voltage (i-v) characteristics for the pal16r8-7 v cc = 5.0 v, t a = 25 c 15 10 output, low i ol , ma 5 C5 C10 C15 C0.6 C0.4 C0.2 0.2 0.4 0.6 v ol , v 20 C40 C60 C80 C3 C2 C1 123 output, high i oh , ma v oh , v C20 input i i , m a v i , v 20 C40 C60 C80 C3 C2 C1 123 C20 16492d-26 16492d-27 16492d-28
amd 2-34 pal16r8-5 input/output equivalent schematics typical input input cc v output typical output 40 w nom input, i/o pins preload circuitry program/verify/ test circuitry program/verify circuitry cc v 16492d-29 16492d-30
amd 2-35 pal16r8 family power-up reset the power-up reset feature ensures that all flip-flops will be reset to low after the device has been powered up. the output state will be high due to the inverting output buffer. this feature is valuable in simplifying state machine initialization. a timing diagram and parameter table are shown below. due to the synchronous opera- tion of the power-up reset and the wide range of ways v cc can rise to its steady state, two conditions are required to ensure a valid power-up reset. these condi- tions are: n the v cc rise must be monotonic. n following reset, the clock input must not be driven from low to high until all applicable input and feed- back setup times are met. parameter symbol parameter description max unit t pr power-up reset time 1000 ns t s input or feedback setup time t wl clock width low t pr t wl t s 4 v v cc power registered active-low output clock 16492d-31 see switching characteristics power-up reset waveform

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